As transistors continue to be designed with ever smaller sub-micron dimensions that require increasingly complex semiconductor fabrication processes to produce, maintaining consistency in the production of those transistors becomes increasingly difficult. This is of particular concern with circuits in which those transistors are used to exchange signals between integrated circuits (ICs) with ever increasing data transmission rates. In particular, as high speed serial input/output (I/O) circuits now reach ever higher data transmission rates, the need for consistency in the production of the transistors used within those high speed serial I/O circuits increases, even as the ability to provide that consistency decreases.
A solution to ensuring such consistency in high speed serial I/O circuits is to test mass produced ICs to determine which ones include high speed serial (I/O) circuits that are able to be operated at the desired higher transmission rates without errors or at least with acceptably low error rates. ICs found to meet such requirements are then sorted out from the ones that do not, and are then used in applications that employ such high transmission rates. Unfortunately, both cost and technical issues have plagued the manner in which such tests have been performed.
Such testing usually entails the connection of expensive test equipment to one or more portions of a high speed serial I/O circuit to observe its behavior as it is tested. However, the shrinking sub-micron dimensions of transistors of these circuits and their operation at such high frequencies both conspire to increase susceptibility to electrical and/or electromagnetic influences that are unavoidably exerted on these circuits through the simple act of connecting such test equipment to them. Much of the expense of such test equipment arises from the effort to carefully design and fabricate components of such test equipment to minimize such influences exerted on such circuits as much as possible, but such influences cannot be completely eliminated. As a result, it is often not possible to rule out electrical and/or electromagnetic influences of such test equipment as the cause of at least a subset of instances in which a high speed I/O circuit fails during such testing. Indeed, the nodes connecting the transistors in such high speed serial I/O circuits must be made with such minimal sub-micron dimensions that adding a gate input of a transistor to such a node can greatly degrade or impeded its ability to convey signals between transistors quickly enough. As a result, even the addition of sub-micron transistors to monitor signal activity in lieu of using external test equipment can undesirably affect the operation of such high speed serial I/O circuits.